Freescale Semiconductor /MK24F12 /SysTick /CSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)ENABLE 0 (0)TICKINT 0 (0)CLKSOURCE 0 (COUNTFLAG)COUNTFLAG

ENABLE=0, TICKINT=0, CLKSOURCE=0

Description

SysTick Control and Status Register

Fields

ENABLE

no description available

0 (0): counter disabled

1 (1): counter enabled

TICKINT

no description available

0 (0): counting down to 0 does not assert the SysTick exception request

1 (1): counting down to 0 asserts the SysTick exception request

CLKSOURCE

no description available

0 (0): external clock

1 (1): processor clock

COUNTFLAG

no description available

Links

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